308 search results - page 30 / 62 » Hardware Reconfigurable Neural Networks |
ASAP
2006
IEEE
14 years 11 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
CEC
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents two variants of Genetic Programming (GP) approaches for intelligent online performance monitoring of electronic circuits and systems. Reliability modeling of el...
FPL
2006
Springer
15 years 1 months ago
2006
Springer
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
ICANN
2007
Springer
15 years 3 months ago
2007
Springer
This work describes a complete indoor location system, from its creation, development and deployment. This location system is a capable way of retrieving the position of wireless d...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...