Sciweavers

308 search results - page 46 / 62
» Hardware Reconfigurable Neural Networks
Sort
View
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
FPL
2000
Springer
116views Hardware» more  FPL 2000»
15 years 1 months ago
FPGA Implementation of a Prototype WDM On-Line Scheduler
Message sequencing and channel assignment are two important aspects to consider in optimizing the performance of Wavelength Division Multiplexing (WDM) networks. A scheduling techn...
Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidz...
FCCM
2007
IEEE
122views VLSI» more  FCCM 2007»
15 years 1 months ago
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...
Ron Sass, William V. Kritikos, Andrew G. Schmidt, ...
FPL
2008
Springer
116views Hardware» more  FPL 2008»
14 years 11 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
IJON
2007
93views more  IJON 2007»
14 years 9 months ago
How much can we trust neural simulation strategies?
Despite a steady improvement of computational hardware, results of numerical simulation are still tightly bound to the simulation tool and strategy used, and may substantially var...
Michelle Rudolph, Alain Destexhe