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» Hardware Reuse at the Behavioral Level
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76
Voted
ISCAS
2005
IEEE
166views Hardware» more  ISCAS 2005»
15 years 3 months ago
Extending SystemC to support mixed discrete-continuous system modeling and simulation
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
Alain Vachoux, Christoph Grimm, Karsten Einwich
68
Voted
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
15 years 2 months ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...
79
Voted
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
15 years 2 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
ISPD
2000
ACM
145views Hardware» more  ISPD 2000»
15 years 2 months ago
A snap-on placement tool
The standard cell placement problem has been extensively studied in the past twenty years. Many approaches were proposed and proven e ective in practice. However, successful place...
Xiaojian Yang, Maogang Wang, Kenneth Eguro, Majid ...
AC
2005
Springer
14 years 9 months ago
Power Analysis and Optimization Techniques for Energy Efficient Computer Systems
Reducing power consumption has become a major challenge in the design and operation of today's computer systems. This chapter describes different techniques addressing this c...
Wissam Chedid, Chansu Yu, Ben Lee