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» Hardware Reuse at the Behavioral Level
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EGH
2004
Springer
15 years 3 months ago
Realtime ray tracing of dynamic scenes on an FPGA chip
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of exist...
Jörg Schmittler, Sven Woop, Daniel Wagner, Wo...
53
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IEEEPACT
2007
IEEE
15 years 4 months ago
A Loop Correlation Technique to Improve Performance Auditing
Performance auditing is an online optimization strategy that empirically measures the effectiveness of an optimization on a particular code region. It has the potential to greatly...
Jeremy Lau, Matthew Arnold, Michael Hind, Brad Cal...
IEEEINTERACT
2003
IEEE
15 years 2 months ago
Compiler-Directed Resource Management for Active Code Regions
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
Ravikrishnan Sree, Alex Settle, Ian Bratt, Daniel ...
WCET
2008
14 years 11 months ago
Traces as a Solution to Pessimism and Modeling Costs in WCET Analysis
WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modificatio...
Jack Whitham, Neil C. Audsley
CORR
2006
Springer
112views Education» more  CORR 2006»
14 years 9 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...