398 search results - page 60 / 80 » Hardware Reuse at the Behavioral Level |
ISCA
1999
IEEE
15 years 4 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
ISCA
1996
IEEE
15 years 4 months ago
1996
IEEE
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
118
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JCPHY
2011
14 years 2 months ago
2011
The calculation of radial distribution functions (RDFs) from molecular dynamics trajectory data is a common and computationally expensive analysis task. The rate limiting step in ...
VLSID
2002
IEEE
16 years 7 days ago
2002
IEEE
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
100
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ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...