398 search results - page 62 / 80 » Hardware Reuse at the Behavioral Level |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
With the increasing levels of variability and randomness in the characteristics and behavior of manufactured nanoscale structures and devices, achieving performance optimization u...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
FPL
2001
Springer
15 years 2 months ago
2001
Springer
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...