398 search results - page 64 / 80 » Hardware Reuse at the Behavioral Level |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
In the absence of a single module interface standard, integration of pre-designed modules in System-on-Chip design often requires the use of protocol converters. Existing approach...
ISLPED
2006
ACM
15 years 3 months ago
2006
ACM
Many techniques have been developed for adaptive power management of computing systems. These techniques rely on the presence of varying power phases to detect opportunities for a...
ACSD
2005
IEEE
15 years 3 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
CODES
2003
IEEE
15 years 2 months ago
2003
IEEE
Hardware/Software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time acc...
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...