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    ERSA
    2009
    185views Hardware» more  ERSA 2009»
    Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
    14 years 9 months ago
    Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
    Download  homepages.uni-paderborn.de
    In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
    Mariusz Grad, Christian Plessl
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    93
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    VLSI
    2007
    Springer
    114views Software Engineering» more  VLSI 2007»
    An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor
    15 years 5 months ago
    An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor
    Download  qir.kyushu-u.ac.jp
    Replacing functional units of an extensible processor with reconfigurable functional units enhances performance and flexibility of processors to execute custom instructions. That ...
    Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Za...
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    89
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    MAM
    2006
    125views more  MAM 2006»
    Stream computations organized for reconfigurable execution
    14 years 11 months ago
    Stream computations organized for reconfigurable execution
    Download  www.cs.berkeley.edu
    Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the f...
    André DeHon, Yury Markovsky, Eylon Caspi, M...
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    TVLSI
    2002
    130views more  TVLSI 2002»
    HW/SW codesign techniques for dynamically reconfigurable architectures
    14 years 11 months ago
    HW/SW codesign techniques for dynamically reconfigurable architectures
    Download  www.csie.ntu.edu.tw
    Abstract--Hardward/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digitalsystems design. However, no previous work has been carried out ...
    Juanjo Noguera, Rosa M. Badia
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    74
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    FPL
    2008
    Springer
    96views Hardware» more  FPL 2008»
    Low-latency high-bandwidth HW/SW communication in a virtual memory environment
    15 years 1 months ago
    Low-latency high-bandwidth HW/SW communication in a virtual memory environment
    Download  www.esa.informatik.tu-darmstadt.de
    Adaptive computers combine conventional software programmable processors with reconfigurable compute units. We present techniques that allow the high-performance realization of de...
    Holger Lange, Andreas Koch
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