We systematically evaluate the performance of five implementations of a single, user-level communication interface. Each implementation makes different architectural assumptions ...
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
We propose signature-accelerated transactional memory (SigTM), a hybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the r...
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Au...
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...