139 search results - page 12 / 28 » Hardware Software Instruction Set Configurability for System... |
ISCA
2006
IEEE
15 years 5 months ago
2006
IEEE
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
FPGA
2004
ACM
15 years 5 months ago
2004
ACM
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
117
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APCSAC
2001
IEEE
15 years 3 months ago
2001
IEEE
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
104
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ICCAD
2001
IEEE
15 years 8 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
105
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TDSC
2010
14 years 6 months ago
2010
We describe Instruction-Set Randomization (ISR), a general approach for safeguarding systems against any type of code-injection attack. We apply Kerckhoffs' principle to creat...