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CGO
2010
IEEE
15 years 4 months ago
Taming hardware event samples for FDO compilation
Feedback-directed optimization (FDO) is effective in improving application runtime performance, but has not been widely adopted due to the tedious dual-compilation model, the difï...
Dehao Chen, Neil Vachharajani, Robert Hundt, Shih-...
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
15 years 8 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
15 years 1 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
DATE
2006
IEEE
118views Hardware» more  DATE 2006»
15 years 5 months ago
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Hei...
ARCS
2004
Springer
15 years 5 months ago
Cryptonite - A Programmable Crypto Processor Architecture for High-Bandwidth Applications
Cryptographic methods are widely used within networking and digital rights management. Numerous algorithms exist, e.g. spanning VPNs or distributing sensitive data over a shared ne...
Rainer Buchty, Nevin Heintze, Dino Oliva