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MICRO
1998
IEEE
108views Hardware» more  MICRO 1998»
15 years 3 months ago
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
97
Voted
DCC
2007
IEEE
15 years 11 months ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...
CODES
2008
IEEE
15 years 6 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
FPL
2010
Springer
267views Hardware» more  FPL 2010»
14 years 9 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
CODES
2005
IEEE
15 years 5 months ago
Enhanced code density of embedded CISC processors with echo technology
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even ...
Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J....