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ERSA
2006
102views Hardware» more  ERSA 2006»
14 years 11 months ago
Process Isolation for Reconfigurable Hardware
One of the pillars of trust-worthy computing is process isolation, the ability to keep process data private from other processes running on the same device. While embedded operati...
Herwin Chan, Patrick Schaumont, Ingrid Verbauwhede
ICPADS
1994
IEEE
15 years 2 months ago
Delayed Precise Invalidation - A Software Cache Coherence Scheme
: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence sc...
T.-S. Hwang, C.-P. Chung
ASPLOS
2006
ACM
15 years 3 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
DAC
2004
ACM
15 years 11 months ago
Virtual memory window for application-specific reconfigurable coprocessors
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
LCPC
1994
Springer
15 years 2 months ago
Optimizing Array Distributions in Data-Parallel Programs
Data parallel programs are sensitive to the distribution of data across processor nodes. We formulate the reduction of inter-node communication as an optimization on a colored gra...
Krishna Kunchithapadam, Barton P. Miller