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DATE
2005
IEEE
129views Hardware» more  DATE 2005»
15 years 3 months ago
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications
In this paper, the program control unit of an embedded RISC processor is enhanced with a novel zerooverhead loop controller (ZOLC) supporting arbitrary loop structures with multip...
Nikolaos Kavvadias, Spiridon Nikolaidis
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
15 years 2 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 3 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
WORDS
2005
IEEE
15 years 3 months ago
Virtual Networks in an Integrated Time-Triggered Architecture
Depending on the physical structuring of large distributed safety-critical real-time systems, one can distinguish federated and integrated system architectures. This paper investi...
Roman Obermaisser, Philipp Peti, Hermann Kopetz
AC
1998
Springer
14 years 9 months ago
Cellular Automata Models of Self-Replicating Systems
Abstract: Since von Neumann's seminal work around 1950, computer scientists and others have studied the algorithms needed to support self-replicating systems. Much of this wor...
James A. Reggia, Hui-Hsien Chou, Jason D. Lohn