230 search results - page 15 / 46 » Hardware Support for Control Transfers in Code Caches |
115
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SIGMETRICS
1996
ACM
15 years 1 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
ASPLOS
2012
ACM
13 years 5 months ago
2012
ACM
The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to para...
ASPLOS
1998
ACM
15 years 1 months ago
1998
ACM
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
ICCD
1999
IEEE
15 years 1 months ago
1999
IEEE
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
137
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MICRO
2006
IEEE
14 years 9 months ago
2006
IEEE
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...