Sciweavers

86 search results - page 14 / 18
» Hardware Support for Interval Arithmetic
Sort
View
153
Voted
KBSE
2005
IEEE
15 years 9 months ago
Automated test generation for engineering applications
In test generation based on model-checking, white-box test criteria are represented as trap conditions written in a temporal logic. A model checker is used to refute trap conditio...
Songtao Xia, Ben Di Vito, César Muño...
119
Voted
TEC
2002
81views more  TEC 2002»
15 years 3 months ago
Genetic object recognition using combinations of views
We investigate the application of genetic algorithms (GAs) for recognizing real two-dimensional (2-D) or three-dimensional (3-D) objects from 2-D intensity images, assuming that th...
George Bebis, Evangelos A. Yfantis, Sushil J. Loui...
118
Voted
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
15 years 10 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
152
Voted
CASES
2005
ACM
15 years 5 months ago
Exploring the design space of LUT-based transparent accelerators
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
116
Voted
FCCM
1998
IEEE
113views VLSI» more  FCCM 1998»
15 years 8 months ago
PAM-Blox: High Performance FPGA Design for Adaptive Computing
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...
Oskar Mencer, Martin Morf, Michael J. Flynn