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ISCAS
2007
IEEE
121views Hardware» more  ISCAS 2007»
15 years 6 months ago
Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design
Abstract– This paper presents an improved topological algorithm for device-level analog placement with symmetry constraints. Based on the exploration of symmetric-feasible sequen...
Karthik Krishnamoorthy, Sarat C. Maruvada, Florin ...
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
15 years 6 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
104
Voted
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
15 years 3 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
83
Voted
DAGSTUHL
2004
15 years 1 months ago
The Kiel Esterel Processor - A Semi-Custom, Configurable Reactive Processor
The synchronous language Esterel is an established language for developing reactive systems. It gives an abstract, well-defined and executable description of the application, and c...
Xin Li, Reinhard von Hanxleden
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
14 years 10 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...