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» Hardware Support for Secure Processing in Embedded Systems
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CASES
2005
ACM
15 years 6 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
MOBIQUITOUS
2008
IEEE
15 years 10 months ago
A secure middleware for wireless sensor networks
SMEPP Light is a middleware for Wireless Sensor Networks (WSNs) based on mote-class sensors. It is derived from the specification developed under the framework of the SMEPP proje...
Claudio Vairo, Michele Albano, Stefano Chessa
ASAP
1997
IEEE
92views Hardware» more  ASAP 1997»
15 years 7 months ago
Optimized software synthesis for synchronous dataflow
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable ...
Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward...
ISCA
2010
IEEE
170views Hardware» more  ISCA 2010»
15 years 9 months ago
Relax: an architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaral...
CASES
2006
ACM
15 years 10 months ago
Automated compile-time and run-time techniques to increase usable memory in MMU-less embedded systems
Random access memory (RAM) is tightly-constrained in many embedded systems. This is especially true for the least expensive, lowest-power embedded systems, such as sensor network ...
Lan S. Bai, Lei Yang, Robert P. Dick