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ISSS
1996
IEEE
143views Hardware» more  ISSS 1996»
15 years 8 months ago
DSP Processor/Compiler Co-Design: A Quantitative Approach
In the paper the problem of processor/compiler codesign for digital signal processing and embedded SYstems is discussed. The main principle we follow is the top-down approach char...
Vojin Zivojnovic, Stefan Pees, C. Schälger, M...
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
15 years 9 months ago
Constrained Power Management: Application to a multimedia mobile platform
—In this paper we provide an overview of CPM, a cross-layer framework for Constrained Power Management, and we present its application on a real use case. This framework involves...
Patrick Bellasi, Stefano Bosisio, Matteo Carnevali...
DATE
2006
IEEE
135views Hardware» more  DATE 2006»
15 years 10 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
15 years 11 months ago
Overcoming limitations of the SystemC data introspection
—Today verification, testing and debugging of SystemC models can be applied at an early stage in the design process. To support these techniques gaining required information of ...
Christian Genz, Rolf Drechsler
CASES
2009
ACM
15 years 11 months ago
Fine-grain performance scaling of soft vector processors
Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...