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» Hardware Support for Secure Processing in Embedded Systems
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GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
15 years 9 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
DATE
2010
IEEE
183views Hardware» more  DATE 2010»
15 years 2 months ago
Toward optimized code generation through model-based optimization
—Model-Based Development (MBD) provides an al level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic tr...
Asma Charfi, Chokri Mraidha, Sébastien G&ea...
ISCAS
2007
IEEE
103views Hardware» more  ISCAS 2007»
15 years 10 months ago
A Low-cost and High-performance SoC Design for OMA DRM2 Applications
A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several...
Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
15 years 10 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...