681 search results - page 11 / 137 » Hardware Synthesis Using SAFL and Application to Processor D... |
FPL
2010
Springer
14 years 7 months ago
2010
Springer
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
IEAAIE
1999
Springer
15 years 1 months ago
1999
Springer
This paper introduces a new approach in the debugging of hardware designs. The design is given as a VHDL program and converted in a component connection model. The conversion is si...
ICIP
2002
IEEE
15 years 11 months ago
2002
IEEE
The JPEG-LS algorithm is one of the recently designated standards for lossless compression of grayscale and color images. In this paper, simulation results for lossless and near l...
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VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
15 years 10 months ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
ICPP
2009
IEEE
15 years 4 months ago
2009
IEEE
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...