Sciweavers

681 search results - page 123 / 137
» Hardware Synthesis Using SAFL and Application to Processor D...
Sort
View
MJ
2011
288views Multimedia» more  MJ 2011»
14 years 4 months ago
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute...
Pablo Garcia Del Valle, David Atienza
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
15 years 6 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
ASPLOS
2009
ACM
15 years 10 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
92
Voted
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
15 years 4 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta
ICPADS
2006
IEEE
15 years 3 months ago
Memory and Network Bandwidth Aware Scheduling of Multiprogrammed Workloads on Clusters of SMPs
Symmetric Multiprocessors (SMPs), combined with modern interconnection technologies are commonly used to build cost-effective compute clusters. However, contention among processor...
Evangelos Koukis, Nectarios Koziris