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ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
15 years 2 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
15 years 1 months ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona
FPL
2003
Springer
95views Hardware» more  FPL 2003»
15 years 2 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
ICCAD
1994
IEEE
116views Hardware» more  ICCAD 1994»
15 years 1 months ago
Design of heterogeneous ICs for mobile and personal communication systems
{ Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of exibility, performance and power...
Gert Goossens, Ivo Bolsens, Bill Lin, Francky Catt...
DSD
2009
IEEE
145views Hardware» more  DSD 2009»
15 years 4 months ago
High Performance Image Processing on a Massively Parallel Processor Array
Multicore and manycore processors are the new wave of computing, offering high performance by using large numbers of simple processors. In this paper, we describe the implementati...
Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bru...