Sciweavers

681 search results - page 23 / 137
» Hardware Synthesis Using SAFL and Application to Processor D...
Sort
View
CASES
2005
ACM
14 years 11 months ago
Exploring the design space of LUT-based transparent accelerators
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
FDL
2003
IEEE
15 years 2 months ago
Object-Oriented ASIP Design and Synthesis
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
15 years 2 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
15 years 6 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
IESS
2007
Springer
110views Hardware» more  IESS 2007»
15 years 3 months ago
Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities
: The performance of feasibility tests is crucial in many applications. When using feasibility tests online only a limited amount of analysis time is available. Run-time efficiency...
Karsten Albers, Frank Bodmann, Frank Slomka