681 search results - page 32 / 137 » Hardware Synthesis Using SAFL and Application to Processor D... |
FPL
2009
Springer
15 years 2 months ago
2009
Springer
This paper presents a reconfigurable processor designed to execute user-defined block-matching motion estimation algorithms, and a toolset for the design of such algorithms and ...
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
ASAP
2004
IEEE
15 years 1 months ago
2004
IEEE
Distributed local memories, or scratchpads, have been shown to effectively reduce cost and power consumption of application-specific accelerators while maintaining performance. Th...
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MICRO
2007
IEEE
15 years 3 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...