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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 9 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
FPL
2003
Springer
128views Hardware» more  FPL 2003»
15 years 2 months ago
A Generic Architecture for Integrated Smart Transducers
Abstract. A smart transducer network hosts various nodes with different functionality. Our approach offers the possibility to design different smart transducer nodes as a system...
Martin Delvai, Ulrike Eisenmann, Wilfried Elmenrei...
GLVLSI
2006
IEEE
126views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
Sathish Chandra, Francesco Regazzoni, Marcello Laj...
ESTIMEDIA
2009
Springer
14 years 7 months ago
Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs
As single-processor systems are ceasing to scale effectively, multi-processor systems are becoming more and more popular. While there are many challenges of designing multi-process...
Wolfgang Haid, Lars Schor, Kai Huang, Iuliana Baci...
CBSE
2005
Springer
15 years 3 months ago
Real-Time Scheduling Techniques for Implementation Synthesis from Component-Based Software Models
We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...
Zonghua Gu, Zhimin He