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107
Voted
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
14 years 8 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
15 years 3 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
86
Voted
DATE
2009
IEEE
114views Hardware» more  DATE 2009»
15 years 4 months ago
Hardware aging-based software metering
Abstract—Reliable and verifiable hardware, software and content usage metering (HSCM) are of primary importance for wide segments of e-commerce including intellectual property a...
Foad Dabiri, Miodrag Potkonjak
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
15 years 4 months ago
Sizing Rules for Bipolar Analog Circuit Design
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level o...
Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
RV
2009
Springer
155views Hardware» more  RV 2009»
15 years 2 months ago
Hardware Supported Flexible Monitoring: Early Results
Monitoring of software’s execution is crucial in numerous software development tasks. Current monitoring efforts generally require extensive instrumentation of the software or d...
Antonia Zhai, Guojin He, Mats Per Erik Heimdahl