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CASES
2003
ACM
15 years 2 months ago
AES and the cryptonite crypto processor
CRYPTONITE is a programmable processor tailored to the needs of crypto algorithms. The design of CRYPTONITE was based on an in-depth application analysis in which standard crypto ...
Dino Oliva, Rainer Buchty, Nevin Heintze
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
15 years 6 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
15 years 1 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 3 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
68
Voted
ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
15 years 4 months ago
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
Praveen Raghavan, José L. Ayala, David Atie...