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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 2 months ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...
HIPEAC
2007
Springer
15 years 3 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
CODES
2005
IEEE
15 years 3 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
79
Voted
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 1 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
61
Voted
DATE
2010
IEEE
127views Hardware» more  DATE 2010»
15 years 2 months ago
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis
— Pattern recognition has many applications in design automation. A generalized pattern recognition algorithm is presented in this paper which can efficiently extract similar pat...
Jason Cong, Hui Huang, Wei Jiang