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CODES
2005
IEEE
15 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
15 years 1 months ago
Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads
Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these diffe...
Kimberly Keeton, David A. Patterson, Yong Qiang He...
IPPS
2009
IEEE
15 years 4 months ago
Performance projection of HPC applications using SPEC CFP2006 benchmarks
Performance projections of High Performance Computing (HPC) applications onto various hardware platforms are important for hardware vendors and HPC users. The projections aid hard...
Sameh Sharkawi, Don DeSota, Raj Panda, Rajeev Indu...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
15 years 4 months ago
Retargetable Code Optimization for Predicated Execution
Retargetable C compilers are key components of today’s embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exp...
Manuel Hohenauer, Felix Engel, Rainer Leupers, Ger...
ASAP
2008
IEEE
105views Hardware» more  ASAP 2008»
14 years 11 months ago
Fast custom instruction identification by convex subgraph enumeration
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. &Ou...