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ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
122
Voted
ISCA
2008
IEEE
205views Hardware» more  ISCA 2008»
15 years 4 months ago
VEAL: Virtualized Execution Accelerator for Loops
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
Nathan Clark, Amir Hormati, Scott A. Mahlke
ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
15 years 2 months ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
15 years 2 months ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
ARITH
2007
IEEE
15 years 4 months ago
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
Liang-Kai Wang, Michael J. Schulte