Sciweavers

681 search results - page 79 / 137
» Hardware Synthesis Using SAFL and Application to Processor D...
Sort
View
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 3 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
MVA
1992
170views Computer Vision» more  MVA 1992»
14 years 10 months ago
An Host-Target Environment for Real Time Image Processing
The development of a real time image processing on a specific architecture is always restricting for the user who must master all the elementary mechanisms of the machine. Such sp...
M. Pizzocaro
72
Voted
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
15 years 2 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
CODES
2006
IEEE
15 years 3 months ago
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
Dong-Ik Ko, Shuvra S. Bhattacharyya
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
14 years 7 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...