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AES
2000
Springer
98views Cryptology» more  AES 2000»
15 years 2 months ago
How Well Are High-End DSPs Suited for the AES Algorithms? AES Algorithms on the TMS320C6x DSP
The National Institute of Standards and Technology (NIST) has announced that one of the design criteria for the Advanced Encryption Standard (AES) algorithm was the ability to eï¬...
Thomas J. Wollinger, Min Wang, Jorge Guajardo, Chr...
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DATE
2007
IEEE
110views Hardware» more  DATE 2007»
15 years 4 months ago
Reconfigurable system-on-chip data processing units for space imaging instruments
Individual Data Processing Units (DPUs) are commonly used for operational control and specific data processing of scientific space instruments. To overcome the limitations of trad...
Björn Fiethe, Harald Michalik, C. Dierker, Bj...
IPPS
2002
IEEE
15 years 2 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
CODES
2005
IEEE
15 years 3 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
TVLSI
2008
108views more  TVLSI 2008»
14 years 9 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu