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» Hardware Synthesis for Asynchronous Communications Mechanism...
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ICCD
2000
IEEE
99views Hardware» more  ICCD 2000»
15 years 8 months ago
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
We present a local clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global clock. After initial tuning, the local clock remains calibr...
Simon W. Moore, George S. Taylor, Paul A. Cunningh...
JSAC
2006
100views more  JSAC 2006»
14 years 11 months ago
Backbone Topology Synthesis for Multiradio Mesh Networks
Wireless local area network (WLAN) systems are widely implemented today to provide hot-spot coverage. Operated typically in an infrastructure mode, each WLAN is managed by an acces...
Laura Huei-jiun Ju, Izhak Rubin
ASYNC
2004
IEEE
102views Hardware» more  ASYNC 2004»
15 years 3 months ago
Non-Uniform Access Asynchronous Register Files
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
David Fang, Rajit Manohar
ICCAD
2008
IEEE
133views Hardware» more  ICCAD 2008»
15 years 8 months ago
Module locking in biochemical synthesis
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...
Brian Fett, Marc D. Riedel
ICECCS
1997
IEEE
97views Hardware» more  ICECCS 1997»
15 years 3 months ago
A Synthesis Method for Fault-tolerant and Flexible Multipath Routing Protocols
Design of practical routing protocols is complex and dificult due to complicated requirements of faulttolerance and flexibility. The protocol is defined to be fault-tolerant if me...
Yutaka Hatanaka, Masahide Nakamura, Yoshiaki Kakud...