339 search results - page 12 / 68 » Hardware Synthesis for Multi-Dimensional Time |
104
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DAC
1994
ACM
15 years 4 months ago
1994
ACM
Existing software scheduling techniques limit the functions that can be implemented in software to those with a restricted class of timing constraints, in particular those with a c...
69
Voted
ICCAD
2007
IEEE
15 years 9 months ago
2007
IEEE
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
ICCAD
2008
IEEE
15 years 9 months ago
2008
IEEE
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
99
Voted
ICCAD
2001
IEEE
15 years 9 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
138
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ISPD
2012
ACM
13 years 8 months ago
2012
ACM
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...