Sciweavers

339 search results - page 14 / 68
» Hardware Synthesis for Multi-Dimensional Time
Sort
View
DATE
2010
IEEE
136views Hardware» more  DATE 2010»
15 years 5 months ago
Reversible logic synthesis through ant colony optimization
Abstract—We propose a novel synthesis technique for reversible logic based on ant colony optimization (ACO). In our ACO-based approach, reversible logic synthesis is formulated a...
Min Li, Yexin Zheng, Michael S. Hsiao, Chao Huang
FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 4 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
ISSS
1996
IEEE
102views Hardware» more  ISSS 1996»
15 years 4 months ago
Throughput Optimization in Disk-Based Real-Time Application Specific Systems
Traditionally, application specific computations have been focusing on numerically intensive data manipulation. Modern communications and DSP applications, such as WWW, interactiv...
Stephen Docy, Inki Hong, Miodrag Potkonjak
DAC
2005
ACM
16 years 1 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
ISPD
2003
ACM
88views Hardware» more  ISPD 2003»
15 years 5 months ago
Porosity aware buffered steiner tree construction
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jia...