339 search results - page 17 / 68 » Hardware Synthesis for Multi-Dimensional Time |
ASPDAC
1995
ACM
15 years 4 months ago
1995
ACM
A heuristic algorithm for a given topology of a multiple-source and multiple-sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting bu...
91
Voted
ASYNC
2003
IEEE
15 years 5 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
98
Voted
ITC
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
ASPDAC
2005
ACM
15 years 2 months ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
ASPDAC
2007
ACM
15 years 4 months ago
2007
ACM
Abstract-- The increasing processing power of embedded devices have created the scope for certain applications that could previously be executed in desktop environments only, to mi...