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108
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ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
15 years 4 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
CHARME
1995
Springer
120views Hardware» more  CHARME 1995»
15 years 4 months ago
Timing analysis of asynchronous circuits using timed automata
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
Oded Maler, Amir Pnueli
92
Voted
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
15 years 6 months ago
Synthesis of Fault-Tolerant Embedded Systems
This work addresses the issue of design optimization for faulttolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpoin...
Petru Eles, Viacheslav Izosimov, Paul Pop, Zebo Pe...
DATE
2000
IEEE
97views Hardware» more  DATE 2000»
15 years 4 months ago
Layout-Oriented Synthesis of High Performance Analog Circuits
This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout con...
Mohamed Dessouky, Marie-Minerve Louërat, Jack...
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
15 years 9 months ago
Guaranteeing performance yield in high-level synthesis
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current hi...
Wei-Lun Hung, Xiaoxia Wu, Yuan Xie