339 search results - page 24 / 68 » Hardware Synthesis for Multi-Dimensional Time |
GLVLSI
2006
IEEE
15 years 6 months ago
2006
IEEE
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
106
Voted
GLVLSI
2008
IEEE
15 years 6 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
104
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DATE
1999
IEEE
15 years 4 months ago
1999
IEEE
Commonly used scheduling algorithms in high-level synthesis only accept one process at a time and are not capable of sharing resources across process boundaries. This results in t...
86
Voted
ISLPED
1997
ACM
15 years 4 months ago
1997
ACM
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
ICECCS
2007
IEEE
15 years 4 months ago
2007
IEEE
Traditional, standards-based approaches to certification are hugely expensive, of questionable credibility when development is outsourced, and a barrier to innovation. This paper ...