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ASPDAC
2008
ACM
87views Hardware» more  ASPDAC 2008»
15 years 2 months ago
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional...
Tsuyoshi Sadakata, Yusuke Matsunaga
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
15 years 4 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
15 years 2 months ago
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block sel
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
Jui-Yuan Hsieh, Shanq-Jang Ruan
ECBS
1996
IEEE
155views Hardware» more  ECBS 1996»
15 years 4 months ago
Model-Integrated Program Synthesis Environment
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
Janos Sztipanovits, Gabor Karsai, Hubertus Franke
99
Voted
DATE
2007
IEEE
72views Hardware» more  DATE 2007»
15 years 6 months ago
The impact of loop unrolling on controller delay in high level synthesis
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan ...