Sciweavers

339 search results - page 28 / 68
» Hardware Synthesis for Multi-Dimensional Time
Sort
View
89
Voted
ISCAS
1999
IEEE
114views Hardware» more  ISCAS 1999»
15 years 4 months ago
Nonuniformly offset polyphase synthesis of a bandpass signal from complex-envelope samples
In this paper we consider the synthesis of a bandpass signal from complex-envelope samples using a polyphase conversion structure based on periodically nonuniform output samples. ...
D. Scholnik, J. O. Coleman
100
Voted
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
15 years 4 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
116
Voted
DAC
1989
ACM
15 years 4 months ago
Scheduling and Binding Algorithms for High-Level Synthesis
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
Pierre G. Paulin, John P. Knight
ASPDAC
1995
ACM
85views Hardware» more  ASPDAC 1995»
15 years 4 months ago
High-level synthesis scheduling and allocation using genetic algorithms
In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies base...
Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen ...
ACSD
2006
IEEE
109views Hardware» more  ACSD 2006»
15 years 2 months ago
Synthesis of Synchronous Interfaces
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
Purandar Bhaduri, S. Ramesh