339 search results - page 30 / 68 » Hardware Synthesis for Multi-Dimensional Time |
104
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ASPDAC
2008
ACM
15 years 2 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
108
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ICCAD
1998
IEEE
15 years 4 months ago
1998
IEEE
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
87
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ISPD
2003
ACM
15 years 5 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
83
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DAC
1999
ACM
16 years 1 months ago
1999
ACM
? The economic viability of the reusable core-based design paradigm depends on the development of techniques for intellectual property protection. We introduce the first dynamic wa...
93
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...