339 search results - page 34 / 68 » Hardware Synthesis for Multi-Dimensional Time |
93
Voted
ASYNC
2004
IEEE
15 years 4 months ago
2004
IEEE
This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesi...
96
Voted
ICCAD
2003
IEEE
15 years 9 months ago
2003
IEEE
In this paper, we present a reduced order inodeling methodology, based on the utilization of optimal non-uniform grids generated by Gaussian spectral rules, for the direct passive...
100
Voted
ICCAD
2000
IEEE
15 years 4 months ago
2000
IEEE
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
109
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ASPDAC
2005
ACM
15 years 2 months ago
2005
ACM
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
137
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ICCAD
2010
IEEE
14 years 10 months ago
2010
IEEE
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...