339 search results - page 39 / 68 » Hardware Synthesis for Multi-Dimensional Time |
108
Voted
ICCAD
2004
IEEE
15 years 9 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
102
Voted
ISPD
2003
ACM
15 years 5 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
82
Voted
ICCD
2007
IEEE
15 years 9 months ago
2007
IEEE
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...
95
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
100
Voted
DATE
2010
IEEE
15 years 5 months ago
2010
IEEE
—The growing trend towards using component based design approach in embedded system development requires addressing newer system engineering challenges. These systems are usually...