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121
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ASPDAC
1998
ACM
105views Hardware» more  ASPDAC 1998»
15 years 4 months ago
Techniques for Functional Test Pattern Execution
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
Inki Hong, Miodrag Potkonjak
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
15 years 7 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
131
Voted
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
15 years 6 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
88
Voted
ASPDAC
2007
ACM
129views Hardware» more  ASPDAC 2007»
15 years 4 months ago
ECO-system: Embracing the Change in Placement
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
Jarrod A. Roy, Igor L. Markov
ICCAD
2007
IEEE
165views Hardware» more  ICCAD 2007»
15 years 4 months ago
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips
Due to the recent advances in microfluidics, digital microfluidic biochips are expected to revolutionize laboratory procedures. One critical problem for biochip synthesis is the dr...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang