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ASPDAC
2008
ACM
134views Hardware» more  ASPDAC 2008»
15 years 2 months ago
Automatic re-coding of reference code into structured and analyzable SoC models
The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are...
Pramod Chandraiah, Rainer Dömer
VTS
2003
IEEE
122views Hardware» more  VTS 2003»
15 years 5 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
99
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ICCAD
2002
IEEE
124views Hardware» more  ICCAD 2002»
15 years 9 months ago
Symbolic pointer analysis
— One of the bottlenecks in the recent movement of hardware synthesis from behavioral C programs is the difficulty in reasoning about runtime pointer values at compile time. The...
Jianwen Zhu
ICCAD
1999
IEEE
76views Hardware» more  ICCAD 1999»
15 years 4 months ago
Optimal allocation of carry-save-adders in arithmetic optimization
: Carry-save-adder(CSA) is one of the most widely used schemes for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocatio...
Junhyung Um, Taewhan Kim, C. L. Liu
ISSS
1998
IEEE
96views Hardware» more  ISSS 1998»
15 years 4 months ago
Fine Grain Incremental Rescheduling Via Architectural Retiming
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
Soha Hassoun