339 search results - page 55 / 68 » Hardware Synthesis for Multi-Dimensional Time |
109
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ERSA
2004
15 years 1 months ago
2004
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
ICCAD
2001
IEEE
15 years 9 months ago
2001
IEEE
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
106
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DDECS
2008
IEEE
15 years 6 months ago
2008
IEEE
: We propose a simple and fast two-level minimization algorithm for completely specified functions in this paper. The algorithm is based on processing ternary trees. A ternary tree...
116
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FPL
2004
Springer
15 years 5 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
100
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DATE
2010
IEEE
15 years 5 months ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...