339 search results - page 57 / 68 » Hardware Synthesis for Multi-Dimensional Time |
93
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
66
Voted
ASAP
2007
IEEE
15 years 4 months ago
2007
IEEE
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
112
Voted
ISQED
2006
IEEE
15 years 6 months ago
2006
IEEE
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
MSE
1999
IEEE
15 years 4 months ago
1999
IEEE
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
ICCAD
1996
IEEE
15 years 4 months ago
1996
IEEE
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...