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99
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ITC
1996
IEEE
107views Hardware» more  ITC 1996»
15 years 4 months ago
Orthogonal Scan: Low-Overhead Scan for Data Paths
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
Robert B. Norwood, Edward J. McCluskey
ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
15 years 2 months ago
A wideband hierarchical circuit reduction for massively coupled interconnects
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
89
Voted
DAGSTUHL
2004
15 years 1 months ago
Removing Cycles in Esterel Programs
Abstract. Synchronous programs may contain cyclic signal interdependencies. This prohibits a static scheduling, which limits the choice of available compilation techniques for such...
Jan Lukoschus, Reinhard von Hanxleden
DAC
2006
ACM
16 years 1 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
94
Voted
ASAP
2009
IEEE
141views Hardware» more  ASAP 2009»
15 years 9 months ago
Accelerating a Virtual Ecology Model with FPGAs
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
Julien Lamoureux, Tony Field, Wayne Luk