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ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
15 years 6 months ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
15 years 5 months ago
RTOS Modeling for System Level Design
System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design ...
Andreas Gerstlauer, Haobo Yu, Daniel Gajski
91
Voted
DATE
2010
IEEE
127views Hardware» more  DATE 2010»
15 years 5 months ago
A portable multi-pitch e-drum based on printed flexible pressure sensors
Pressure sensors are ideal candidates for implementing portable digital music instruments. Existing commercial pressure sensors, however, are not optimized to meet both timing and...
Chun-Ming Lo, Tsung-Ching Huang, Cheng-Yi Chiang, ...
ISPD
2000
ACM
97views Hardware» more  ISPD 2000»
15 years 4 months ago
Routability-driven repeater block planning for interconnect-centric floorplanning
In this paper we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and der...
Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
15 years 4 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...